The present invention relates to a parallel-serial conversion circuit. More specifically, this invention relates to a parallel-serial conversion circuit which insures accurate timing between data and clocks in parallel-serial data conversion.
FIG. 7 is a block diagram of a conventional parallel-serial conversion circuit as disclosed, in Japanese Patent Laid-Open Publication No. SHO 60-189330. The parallel-serial conversion circuit 1000 comprises an oscillation circuit 1001 which outputs a clock signal, a frequency divider circuit 1002 which dichotomizes the clock signal. The parallel-serial conversion circuit 1000 further comprises parallel-serial converters 1003, 1004 each having two input terminals, AND circuits 1005, 1006, an inverter circuit 1007, and an OR circuit 1008.
The clock signal output by the oscillation circuit 1001 is dichotomized by the frequency divider circuit 1002. The dichotomized signal is input into the parallel-serial converter 1003. Parallel data A, C is also input into the parallel-serial converter 1003. Serial data is output from the parallel-serial converter 1003.
The dichotomized signal inverted by the inverter circuit 1007 is input into the parallel-serial conversion circuit 1004. Parallel data B and D are also input into the serial-parallel converter 1004. Serial data is output from the serial-parallel converter 1004.
The AND circuits 1005, 1006 calculate the conjugate of the serial data output by the parallel-serial converters 1003, 1004. Serial data is output from the parallel-serial conversion circuit 1000 via the OR circuit 1008.
Consider a case, for instance, in which a parallel signal sent in synchronism with a 125 MHz clock is converted into a serial signal at a ratio of 10 to 1 using only the positive edge of the clock which is input into each of the parallel-serial converters 1003, 1004. Then, in the conventional high speed parallel-serial conversion circuit a high speed clock of 125 MHz xc3x9710 =1.25 GHz is required as a clock to be input into the parallel-serial converters 1003, 1004.
Further, even if both the positive and negative edges of the clock are used, a high speed clock of 125 MHzxc3x9710/2=625 MHz is required.
Use of the high speed clock as described above presents a technological restriction in designing, which is a bottleneck in realization of high speed operations in parallel-serial conversion. Further, even when a high speed clock is not used, the data width is equal to the total width of signals used for selection of data, which requires strict adjustment of timing between data and clocks.
The parallel-serial conversion circuit according to this invention comprises a frequency divider circuit which outputs a dichotomized signal of an input clock signal. A positive edge triggered flip-flop and a negative edge triggered flip-flop receive data and the dichotomized signal are input. A tap signal generator receives the clock signal and generates and outputs a series of tap signals by providing different delays to the clock signal. A selection signal generator receives the tap signals generates a series of pulse signals having the width equivalent to 1 bit of serial data. An inverter circuit inverts the dichotomized signal. A 10-bit parallel-serial converter receives data of the flip-flops, signals of the inverter circuit, and the pulse signals. The 10-bit parallel-serial converter performs parallel to serial conversion based on the input data and signals and outputs the serial data.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.